1. Field of the Invention
This invention relates to a data resister circuit in a memory device, and more particularly to a data register circuit for preventing the malfunction of a memory device by preventing the previously stored data in a register from changing due to noise and frequency increase before reset.
2. Description of the Related Art
FIG. 1 shows a circuit diagram of a data register circuit in a memory device in the prior art. The data register circuit includes a data input portion 10 for receiving data signals, a data storing portion 20 for storing the data signal from the data input portion 10, and a data output portion 30 for providing a data stored in the data storing portion 20.
The input portion 10 includes a first input stage 12 for receiving the data signal DATA transferred through a data line and a second input stage 14 for receiving a data bar signal DATAb transferred through a data bar line. The first input stage 12 includes PMOS transistors P1 and P2 and a NMOS transistor N1. The PMOS transistors P1 and P2 are connected between a power supply Vcc and an output node Nd1 of the first input stage 12 in series and are activated by a data fetch signal DATA_FETCH and the data signal DATA from the data line, respectively. The data fetch signal DATA_FETCH is a command signal for making data into store into a register. The MNMOS transistor N1 is connected between a ground Vss and the output node Nd1 of the first input stage 12 and is activated by a data reset signal DATA_RESET.
The second input stage 14 includes PMOS transistors P3 and P4 and a NMOS transistor N2. The PMOS transistors P3 and P4 are connected between a power supply Vcc and an output node Nd2 of the second input. stage 14 in series and are activated by the data fetch signal DATA_FETCH and the data bar signal DATAb, respectively. The NMOS transistor N2 is connected between the output node Nd2 and the ground Vss and is activated by the data reset signal DATA_RESET.
At initial operation, the data input portion 10 including the first and second input stages 12 and 14 resets the potentials of the output nodes Nd1 and Nd2 at a low state by the data reset signal DATA_RESET. If the data signal is received, the first or second input stage 12 or 14 is activated by the data fetch signal DATA_FETCH of a low state. If the data signal DATA is a low state, the first input stage 12 are activated so that the output node Nd1 of the first input stage 12 becomes at a high state. At this time, the second input stage 14 is not activated and the output node Nd2 of the second input stage 14 becomes at a low state.
If the data signal DATA is a high state, the data bar signal DATAb becomes at a low state and the second input stage 14 is activated so that the output node Nd2 of the second input stage 14 becomes at a high state. At this time, the first input stage 12 is not activated and the output node Nd1 of the first input stage 12 becomes at a low state.
On the other hand, the data storing portion 20 includes a first latch for temporarily storing an output signal Nd1 of the first input stage 12 and a second latch for temporarily an output signal Nd2 of the second input stage 14. The first latch includes inverters INV3 and INV4 which are connected to the output node Nd1 of the first input stage 12 in parallel. The second latch includes inverters INV1 and INV2 which are connected to the output node Nd2 of the second input stage 14 in parallel. The data storing portion 20 further includes a NAND gate NA2 for carrying out logic NAND operation of the output signal Nd2 of the second input stage 14 and an output signal Nd4 of the first latch to generate an output signal to a node Nd6 and a NAND gate NA1 for carrying out logic NAND operation of an output signal Nd3 of the second input latch and the output signal Nd1 of the first input stage 12.
The data output portion 30 includes a first output stage 32 and a second output stage 34 for providing the output signals Nd6 and ND5 from the data storing portion 20 to a pull-up terminal pu and a pull-down terminal pd, respectively in accordance with a data output control signal DATA_out.
The first output stage 32 of the data output portion 30 includes PMOS transistors P5 and P6 which are connected between the power supply Vcc and the pull-down terminal pd in series and activated by the output signal Nd5 of the data storing portion 20 and an inverted signal of the output control signal DATA_out through an inverter IN35, respectively and NMOS transistors N3 and N4 which are connected between the pull-down terminal pd and the ground Vss and activated by the output control signal DATA_out and the output signal Nd2 of the second input stage 14 of the data input portion 10, respectively.
The second output stage 34 of the data output portion 30 includes PMOS transistors P7 and P8 which are connected between the power supply Vcc and the pull-up terminal pu in series and activated by the output signal Nd6 of the data storing portion 20 and the inverted signal of the output control signal DATA_out, respectively and NMOS transistors N5 and N6 which are connected between the pull-up terminal pu and the ground Vss and activated by the output control signal DATA_out and the output signal Nd1 of the first input stage 12 of the data input portion 10, respectively.
The operation of the data register circuit will be described as follows. Before the data signal is received, all the output nodes Nd1 and Nd2 of the first and second input stages 12 and 14 have potentials of low state by the data reset signal DATA_RESET which is a command signal for resetting the data stored in the register.
If the data of low state is received, the output node Nd1 of the first input stage 12 maintains at a high state and the output node Nd2 of the second input stage 14 maintains at a low state by the data fetch signal DATA_FETCH of low state. Accordingly, the output nodes Nd5 and Nd6 of the data storing portion 20 become a low state and a high state, respectively.
If the data output control signal DATA_out becomes a high state, the register circuit outputs a high state signal and a low state signal through the pull-down terminal pd and the pull-up terminal pu, respectively.
However, the data register circuit in a memory device has disadvantage as follows. After data has been stored in a register, if another data is received due to noise or crosstalk, the previous date stored in a register is lost, thereby occurring the malfunction. Besides, there is no time margin to appropriately separate the consecutive two data with the increase of frequency so that the data is lost. In other words, the previous data is completely received in one register and then the present data should be stored in another register. When the frequency is increased, because the consecutive two data do not appropriately separated, the previous data and the present data are concurrently stored into the same register so that the previous data is lost.
The above problem will be described with reference to FIG. 1. When the data signal DATA of low state is received, the data bar signal DATAb of low state is also received due to noise, crosstalk or the increase of frequency, the signal stored in a register is changed and the output signals pu and pd become all low states so that it does not provide the data.